000			00459nam a2200145Ia 4500
100			_aMule, A.R. _914313
700			_a Subbaraman, S. [Guide] _914314
250			_a1st Ed.
365			_cRs.
942			_cD
245			_aDesign and Fpga Implementation of Low Latency Dynamic and Modified Dynamic Lottery Bus Arbitration Algorithm for on Chip Communication
260			_bWalchand College of Engineering _aSangli _c2018
082			_bMUL
300			_aviii, 40 p.
999			_c57347 _d57347
546			_aText in English
041			_aeng
300			_c20 cm.