Ajit Gulabchand Central Library, Walchand College Of Engineering Sagli


   Ajit Gulabchand Central Library,
Walchand College Of Engineering Sangli

Design and Fpga Implementation of Low Latency Dynamic and Modified Dynamic Lottery Bus Arbitration Algorithm for on Chip Communication

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Walchand College of Engineering Sangli 2018Edition: 1st EdDescription: viii, 40 p; 20 cmDDC classification:
  • MUL
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Holdings
Item type Current library Collection Call number Status Barcode
Dissertation Walchand College of Engineering sangli ELN MUL (Browse shelf(Opens below)) Available D02878

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