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Embedded Software Verification Using State Machine Synthesis

Patil, M. M.

Embedded Software Verification Using State Machine Synthesis - 1st Ed. - Sangli Walchand College of Engineering 2006 - 250 p. 20 cm.

Text in English

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Ajit Gulabchand Central Library, Walchand College Of Engineering Sangli

Embedded Software Verification Using State Machine Synthesis

Ajit Gulabchand Central Library,
Walchand College Of Engineering Sangli